1. Field of the Invention
The present invention generally relates to a circuit design, and more particularly to an electrostatic discharge protection circuit.
2. Description of the Prior Art
For some reasons, for instance, to save layout area and to enlarge parasitic capacitance, result in serious problem of electrostatic discharges (ESD) in the fabrication process. With the progress of the process, the effects of electrostatic discharges are more serious than before. Moreover, the reliability of circuits may be damaged because of electrostatic discharge. For examples, the gate oxide has to become thinner for saving the area or for suiting the characteristic of the components. Then, the LDD structure may be used for resolving the hot-carrier effect problem. The progress technique for saving the area causes the electrostatic discharge protection down, thereby the damage caused by electrostatic discharge increases. More particularly, the thinner the gate oxide is made, the lower the trigger voltage of the oxide is. Thus, how to efficiently drain electrostatic discharge for avoiding the gate suffering damage will be a very important concern.
Referring to FIG. 1A, a gated grounded N-P structure may be used to be an electrostatic discharge protection circuit. The gate oxide of the simple CMOS structure is often damaged by high voltage and the circuit could be unreliable. Thus, a cascade structure, referring to FIG. 1B, two cascade N-MOS, is often used to be an electrostatic discharge protection component in a tolerant I/O circuit to resolve such a problem.
Such an ESD protection component applies the characteristic of “Zener breakdown” of the potential NPN bipolar to drain ESD. The gated grounded N-P structure also has a potential NPN bipolar with a shorter length of the base, because its base is coupled with the ground. Comparing with them, the potential NPN bipolar in the cascade structure has the longer length of the base because of the two cascade N-MOS. The longer base means that it is harder to turn on the potential NPN bipolar. It also means the trigger voltage is higher and the ability for ESD protection decreases. The conventional ESD protection circuit applies the ESD drain circuit to drain ESD, so there are many different designs of the ESD protection circuit, such as N-P structure and cascade structure. Furthermore, ESD protection circuit also needs extra designs to ensure that the ESD is drain toward substrate. It avoids too much current being collected on the surface to cause locally over heat or component damaged.
Accordingly, applying only one ESD drain circuit to drain ESD may suffer the damage by the unexpected current over the predetermined design. But, to strengthen the ESD drain circuit for the problem will cause the ability for ESD protection down. Thus another design, referring to FIG. 1C, applies two parallel ESD drain circuit to share the current. FIG. 1C illustrates the cascade structure to be the ESD protection circuit. The ESD protection circuit can also be the N-P structure and so on. The parallel cascade structures are structured by 4 N-MOS with gate pads A, B, C and D. In this regard, gate pads B and D are electrically coupled with a first level circuit and a resistance E respectively. With the effect of coupling, the amounts of voltage in B and D will be different. Thus, the resistance of the first level circuit and resistance E should match, and thereby the ESD won't be centralized in a single cascade structure to cause locally over heat or component damaged. The foregoing problem does not only happen in the cascade structure, but also other ESD drain circuit.
It is very hard to accurately evaluate the resistance of the first level circuit, and thereby the resistance of E is hard to be matched, whereby the time to drain ESD in each of the parallel ESD drain circuits will be different. Thus ESD may centralize in one ESD drain circuit. However, it is impossible to change resistance E after the circuit is fabricated. For adjusting the resistance, referring to FIG. 1D, an N-MOS can be added for controlling the resistance of E. Such a design makes some improvement, but it still can not accurately evaluate the resistance. Because the resistance of the first level circuit coupled with gate pad B may change with the environment, the resistance E shown in FIG. 1C and the N-MOS shown in FIG. 1D can not completely resolve the foregoing problems. Therefore how to equalize the current to each ESD protection circuit is the key resolve ESD.